1. Field of the Invention
The present invention relates to a sensor driving circuit, a sensor driver device, an image reading apparatus, and an image forming apparatus capable of decreasing influence of skew among signals having different edges.
2. Description of the Related Art
Charge-coupled device (CCD) line image sensors (hereinafter, referred to as “CCD”) have been employed in an image reading apparatus as photoelectric converter for reading images of an original. There may be cases where variation in threshold voltages, and difference in delay time of rise time (hereinafter, “rise delay time”) and in delay time of fall time (hereinafter, “fall delay time”) of a CCD driver that drives the CCD and variation in the difference are not negligible, making it difficult to secure timing appropriately. To this end, techniques of supplying signals, on which timing is stipulated, via a single same driver so as to reduce timing variation (skew) and to secure signal timing have already been known.
For instance, Japanese Patent Laid-open Publication No. H11-177783 discloses a configuration, in which a drive signal, which serves as reference for timing of output signals of a CCD (hereinafter, “CCD output signal”), and an output signal of a sample-and-hold circuit (hereinafter, “sample/hold signal”) in an analog-front-end (AFE) are supplied via a single driver so as to reduce skew between the CCD output signal and the sample/hold signal.
An example of a driving circuit according to a conventional technique is described below.
FIG. 10 is a functional block diagram of a conventional driving circuit that drives a CCD 2 and an AFE 3.
A timing generator (TG) 1 generates various clock signals and gate signals required by the CCD 2 and the AFE 3. A CCD-drive clock signal xCCD_clk, which is one of the output signals of the TG 1, is inputted to the CCD 2 via a CCD driver (hereinafter, “DRV”) 4. Because an inverting driver, which is advantageous in terms of speed, is typically used as the DRV 4, an output signal CCD_CLK of the DRV 4 is inverted relative to the CCD-drive clock signal xCCD_clk in the configuration illustrated in FIG. 10. The CCD 2 outputs an analog image signal SIG. After being buffered in an emitter follower (EF) 5, the analog image signal SIG is inputted to the AFE 3 via a coupling capacitor 6.
The AFE 3 conducts sampling-and-holding, clamping, offset correction, signal amplification, and the like on the analog image signal SIG and the analog image signal SIG is eventually subjected to analog-to-digital (A/D) conversion. The digital image data D is outputted from the AFE 3. Meanwhile, a sample/hold signal SHD supplies a signal xshd that is outputted from the TG 1 to the AFE 3 via the DRV 4.
The sample/hold signal SHD is inverted relative to the signal xshd as in the case described above. The sample/hold signal SHD may not necessarily need to pass through the DRV 4; however, in order to reduce skew between an output signal of the CCD (whose output timing depends on the signal COD_CLK) and the sample/hold signal SHD, the sample/hold signal SHD and the output signal of the CCD are supplied via the same driver in this configuration.
When a stipulation on the timing between a master clock signal in the AFE 3 and the sample/hold signal SHD is relatively less severe, an output signal MCLK of the TG 1 is directly supplied to the AFE 3 in this configuration. However, when the stipulation on the timing is relatively severe, the output signal of the TG 1 may be supplied to the AFE 3 via the DRV 4.
FIG. 11 is an explanatory circuit diagram illustrating details of the driving circuit depicted in FIG. 10. It should be noted that circuits and devices will be described below by way of examples of complementary metal oxide semiconductor (CMOS) circuits and devices. In FIG. 11, capacitance components described on each of the input terminals of the CCD 2 and the AFE 3 indicates that input loads viewed from input pins of an IC device that includes the CCD 2 and the AFE 3 are capacitive loads. In other words, such capacitors are not actually provided at the input terminals.
The CCD-drive clock signal CCD_CLK depicted in FIG. 10 actually includes a plurality of signals, such as charge-transfer clock signals PH1A and PH2A, a last-stage-transfer clock signal PH2L, a resetting clock signal RS, a clamping clock signal CP, and a shift gate signal SH for driving the CCD 2.
As described above with reference to FIG. 10, the sample/hold signal SHD is supplied to the AFE 3 via the DRV 4. In the circuit depicted in FIG. 11, voltage division by using a resistor is performed so as to satisfy an input range for the AFE 3. Outputs of the DRV 4 are connected in parallel to increase drivability of the DRV 4 to drive the charge-transfer clock signals PH1A and PH2A whose loads are relatively large.
The CCD 2 has two channels. A charge-transfer clock signal PH1A for one of the channels and a charge-transfer clock signal PH2A for the other are output from the TG 1 independently. When timing requirement is imposed on signals, skew between the signals is reduced. Accordingly, each pair of signals is configured to be supplied from a single IC device from among a plurality of IC devices that form the DRV 4. Examples of the pair include a pair of charge-transfer clock signals PH1A and PH2A that are to be fed to a first channel, which is one of the channels, a pair of charge-transfer clock signals PH1A and PH2A that are to be fed to a second channel, which is the other one, a pair of the last-stage transfer clock signal PH2L and a resetting clock signal RS, a pair of the resetting clock signal RS and a clamping clock signal CP, a pair of the last-stage transfer clock signal PH2L and the sample/hold signal SHD, and a pair of the resetting clock signal RS and the sample/hold signal SHD. In the example illustrated in FIG. 11, the DRV 4 includes three IC devices, or, more specifically, IC devices DRVa, DRVb, and DRVc.
Resistor-capacitor (RC) circuits for use in timing fine adjustment are provided between the TG1 and the DRV 4, and between the CCD 2 and the AFE 3. In FIG. 11, the CCD output signal SIG is omitted.
Problems in the driving circuit illustrated in FIG. 10 and FIG. 11 are described below.
FIG. 12 is a schematic block diagram for illustrating effects and the problems of the driving circuit according to the conventional technique with timing charts for explaining operations.
As a condition for causing the CCD 2 to operate appropriately, timing of the signals contained in the CCD-drive clock signal CCD_CLK described above, or signal-to-signal timing, is stipulated. For instance, it is required to cause the pair of the charge-transfer clock signal PH1A and the charge-transfer clock signal PH2A to have the voltage (referred to as “crosspoint voltage”), at which the clock signals have the same signal voltage, of 1.5 V or higher. In addition, it is required to ensure at least 4 to 5 nanoseconds (ns) or longer period of time where the voltage difference between the charge-transfer clock signal PH1A and the charge-transfer clock signal PH2A is 4.5 V or higher.
Such stipulation as described above is also set for the charge-transfer clock signal PH1A and the last-stage-transfer clock signal PH2L. Similar stipulation is set also for the resetting clock signal RS, the clamping clock signal CP, and the last-stage-transfer clock signal PH2L. More specifically, timing is stipulated among these signals, and a minimum “high” width is stipulated for each of the resetting clock signal RS and the clamping clock signal CP. It is necessary to satisfy these timing requirements even when there is variation in characteristics of component part. Failure to satisfy these requirements may result in deficiency related to characteristics, such as transfer efficiency or noise.
The block diagram in FIG. 12 illustrates a conventional driving circuit. The timing charts indicated by (A), (B), (C), and (D) in FIG. 12 illustrate relative timing relation by way of an example of the pair of the resetting clock signal RS and the clamping clock signal CP. Referring to FIG. 12, the resetting clock signal RS and the clamping clock signal CP are inputted into the CCD 2 via the DRV 4 in the same package (IC device) as illustrated in FIG. 11.
The signals xrs and xcp that are outputted from the TG 1 are inputted into the DRV 4 via an RC circuit. The signals xrs and xcp are inverted by an inverter circuit in the DRV 4 and outputted from the DRV 4 as the signals RS and CP, which are then inputted into the CCD 2 via a resistor circuit (or an RC circuit).
The phase difference between a rising edge of the signal xrs indicated by “circle” and a rising edge of the signal xcp indicated by “circle” is t2 (see the timing diagram illustrated by (A) of FIG. 12) at a stage outputted from the TG 1. The signals outputted from the TG 1 are inputted into the DRV 4 via the RC circuit. The relation between the rising edge of the signal xrs and the rising edge of the signal xcp remains the same at the input of the DRV 4 (see the timing diagram illustrated by (B) of FIG. 12).
Although outputs (the signals RS and CP) of the DRV 4 are delayed relative to inputs of the DRV 4, because the signals RS and CP have the same fall delay time at the output (hereinafter, “output fall delay time”), the phase difference at the output stage of the DRV 4 remains the same (see the timing diagram illustrated by (C) of FIG. 12). The outputs of the DRV 4 are inputted into the CCD 2 via the resistor circuit. Because the phase difference at the output of the DRV 4 remains the same, the phase difference between the falling edge of the signal RS and the falling edge of the signal CP at the input of the CCD 2 is not changed (see the timing diagram illustrated by (D) of FIG. 12).
In other words, as for the timing between the same rising edges or between the same falling edges (hereinafter, “same edges”), the phase difference at the output stage of the TG 1 is maintained at the input stage of the CCD 2, which allows easy timing adjustment. This is because the signals RS and CP are fed via the single package driver (DRV 4), skew between the falling edge of the signal RS and the falling edge of the signal CP is restrained.
However, similar effect is not achieved with timing between a rising edge and a falling edge (hereinafter, “different edges”), such as timing between the rising edge of the signal xrs indicated by “circle” and the falling edge of the signal xcp indicated by “x.”
The phase difference between the rising edge of the signal xrs and the falling edge of the signal xcp at the output of the TG 1 is t1 (see the timing diagram illustrated by (A) of FIG. 12). The outputs of the TG 1 are inputted into the DRV 4 via the RC circuit. The relation between the rising edge of the signal xrs and the falling edge of the signal xcp is not changed in the DRV 4 (see the timing diagram illustrated by (B) of FIG. 12).
The outputs (the signals RS and CP) of the DRV 4 are delayed relative to the inputs of the DRV 4. In the signal RS “an output fall delay time” is produced, while in the signal CP “an output rise delay time” is produced, which are different from each other. Accordingly, there is produced a relative phase difference corresponding to the difference (Δt) between the output fall delay time and the output rise delay time at the output of the DRV 4. In other words, the phase difference at the input of the DRV 4 is t1, whereas the phase difference at the output of the DRV 4 is t1−Δt (see the timing diagram illustrated by (C) of FIG. 12). Because it is assumed that the output rise delay time is longer than the output fall delay time, the phase difference changes in a decreasing direction.
The outputs of the DRV 4 are inputted into the CCD 2 via the resistor circuit. Because the phase difference remains the same at the output of the DRV 4, the phase difference between the falling edge of the signal RS and the rising edge of the signal CP at the input of the CCD 2 is t1−Δt (see the timing diagram taken at (D) of FIG. 12). This means that skew between the falling edge of the signal RS and the rising edge of the signal CP is not restrained even if the signals RS and CP are supplied via the single package driver (DRV 4).
The phase difference Δt is produced mainly because the output rise delay time (tpLH) and the output fall delay time (tpHL) of the DRV 4 are not equal to each other. This may be expressed as Δt≈tpLH−tpHL. When a CMOS device is used as the DRV 4, tpLH and tpHL depend on characteristics of PMOS (type-transistor) and of NOMOS (type-transistor) at the output stage of the DRV 4. PMOS and NMOS differ from each other in structure (carriers of PMOS are holes whereas carriers of NMOS are electrons whose mobility is larger than that of holes), therefore generally NMOS is more advantageous than PMOS in terms of speed.
More specifically, because the operation speed of NMOS that is turned on at fall of a signal is greater than operation speed of PMOS that is turned on at rise of a signal, tpHL is shorter than tpLH.
It should be noted that when PMOS transistors and NMOS transistors are arranged on a single semiconductor chip as in a typical CMOS semiconductor device, characteristic correlation between the PMOS transistors and correlation between the NMOS transistors exist (in other words, the PMOS transistors are likely to be identical with each other in characteristics and the NMOS transistors are likely to be identical with each other in characteristics), whereas characteristic correlation between a PMOS transistor and a NMOS transistor does not exist (in other words, characteristics of the PMOS transistor and characteristics of the NMOS transistor vary independently of each other).
If signals are inputted to the DRV 4 that is the single package driver (single semiconductor chip), relative phase difference (skew) is not produced between the same edges because the same edges have the same delay time, whereas skew is produced between different edges because of different delay time. As described above, because the characteristics of PMOS and NMOS vary independently of each other, tpLH and tpHL vary independently of each other, causing Δt to vary widely.
As described above, even when signals are inputted via a single package driver, skew between different edges resulting from variation in difference between tpLH and tpHL remains large, which makes it difficult to satisfy signal timing. A relatively fast device whose tpLH and tpHL each is approximately 2 to 6 ns is employed as the DRV 4, even in a situation mentioned above, when tpLH and tpHL vary independently of each other, skew of ±4 ns (8 ns in width) at maximum is produced. When the skew is converted into frequency that may be drivable by CCDs which are currently in a mainstream, it is assumed that upper limit is approximately 25 MHz (half cycle: 20 ns) (more specifically, allowable rise/fall time: 3 ns times 2, allowable variation: 8 ns, and timing-adjustment period: 6 ns). It will be difficult to achieve operation speed higher than this.
Skew resulting from variation in difference between tpLH and tpHL of the DRV 4 has been described above. Not only this variation, but also variation in threshold voltages of the DRV 4 may be a cause of skew.
FIG. 13 is a schematic block diagram with timing charts for illustrating how skew is produced by the threshold voltages (at inputs and outputs of the DRV 4) in the conventional driving circuit. The circuit diagram in FIG. 13 depicts only a portion around the DRV 4 illustrated in FIG. 12.
The threshold voltages are generally defined such that a threshold voltage at rise input (Vtp) and a threshold voltage at fall input (Vtn) differ from each other in a similar way as in the case of the output delay time.
Referring to FIG. 13, the signals xrs and xcp output from the TG 1 (not shown in FIG. 13) are inputted into the DRV 4 (see the timing diagram taken at (B) of FIG. 13). Peak signal level (hereinafter, “high level”) of the output signals xrs and xcp of the TG 1 is the same as that of supply voltage (Vtg) supplied to the TG 1. In the example illustrated in FIG. 13, Vtp is approximately a half of Vtg whereas Vtn is approximately a quarter of Vtg. A period of time from rise start of the signals xrs and xcp to a point in time where the signals reach Vtp may be expressed as approximately 0.69τ, where t is a time constant of the signals. A period of time from fall start of the signals to a point in time where the signals reach Vtn may be expressed as approximately 1.39τ.
Accordingly, the phase difference between a falling edge (indicated by “circle”) of the output signal RS of the DRV 4 and a rising edge (indicated with “x”) of the output signal CP of the DRV 4 produces skew of period that depends on difference in time (hereinafter, “reach time”) at which each signal reaches the corresponding threshold value as in the case of the delay time (see the timing diagram illustrated by (C) of FIG. 13). The thus-produced skew Δt is 0.7τ (=1.39τ−0.69τ), which is obtained based the difference in reach time to the threshold voltages calculated above.
The high level of signals RS and CP outputted from the DRV 4 are converted to the supply voltage (Vdrv) (see the timing diagram illustrated by (C) of FIG. 13), and inputted into the CCD 2 via the resistor circuit (not shown in FIG. 13).
The skew Δt varies depending on variation in the threshold voltages Vtp and Vtn. The range of the variation further depends on the time constant t of the input signals of the DRV 4 because of the relation described above. Put another way, magnitude of influence of the variation in the threshold voltages is proportional to the value of τ.
As described above, as for timing between different edges, skew may be produced not only by difference between tpLH and tpHL but also by variation in the threshold voltages Vtp and Vtn. Although there is more characteristic correlation between the threshold voltages Vtp and Vtn than the characteristic correlation between tpLH and tpHL, the threshold voltages Vtp and Vtn essentially vary independently of each other.
In contrast, skew is not produced by the same edges as in the case of delay time. This is also because correlation between Vtp and Vtp or between Vtn and Vtn is strong (characteristics thereof are substantially identical to each other) while correlation between Vtp and Vtn is weak. Accordingly, so long as the time constant of the signal xrs and the time constant of the signal xcp are substantially equal to each other, even when the threshold voltages vary, the threshold voltages vary in a similar manner, thus skew is subdued.
Note that in the configuration illustrated in FIG. 13, influence exerted by tpLH and tpHL are not taken into consideration to describe skew by the threshold voltages (i.e., it is assumed that tpLH=tpHL=0). Actual skew is produced by a combined total of influence related to the threshold voltages and difference between tpLH and tpHL.
As described above, the conventional technique is disadvantageous in that although the technique allows skew reduction when the skew is produced between same edges (e.g., a rising edge and a rising edge) of signals, on which timing requirement is imposed, the technique cannot attain skew reduction when the skew is produced between different edges (e.g., a rising edge and a falling edge) due to difference between rise delay time and fall delay time at a driver and variation in high-threshold voltage/low-threshold voltage of the driver.